chiranthsiddappa / caf_verilog
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185

Pull #6

travis-ci-com

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Adding other modules that needed changing for arg max
Pull Request #6: Prepend keys

35 of 35 new or added lines in 7 files covered. (100.0%)

883 of 979 relevant lines covered (90.19%)

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979 RELEVANT LINES 883 COVERED LINES
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
185 prepend-keys Adding other modules that needed changing for arg max Pull #6 web-flow travis-ci-com pending completion  
184 prepend-keys Adding other modules that needed changing for arg max push Chiranth Siddappa travis-ci-com pending completion  
183 prepend-keys Moving file into test folder Pull #6 web-flow travis-ci-com pending completion  
182 prepend-keys Moving file into test folder push Chiranth Siddappa travis-ci-com pending completion  
181 unconnected-fix Connecting unconnected wire; still unused push Chiranth Siddappa travis-ci-com pending completion  
180 master Adding notebooks into the toctree push Chiranth Siddappa travis-ci-com pending completion  
179 docs Adding changes for notebook from paper writing push Chiranth Siddappa travis-ci-com pending completion  
178 master Renaiming the xcorr output and using subplot for zoomed in image push Chiranth Siddappa travis-ci-com pending completion  
177 docs Renaiming the xcorr output and using subplot for zoomed in image push Chiranth Siddappa travis-ci-com pending completion  
176 docs Merge branch 'docs' of github.com:chiranthsiddappa/caf_verilog into docs push Chiranth Siddappa travis-ci-com pending completion  
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