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chiranthsiddappa / caf_verilog
76%
master: 90%

Build:
Build:
LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
Repo Added 13 Nov 2018 02:50AM UTC
Files 30
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LAST BUILD ON BRANCH sig-gen
branch: sig-gen
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  • sig-gen
  • argmax
  • caf
  • capture_buffer
  • cpx-multiply
  • docs
  • dot-prod-pip
  • freq_shift
  • master
  • prepend-keys
  • reference_buffer
  • sim-helper
  • sqrt
  • unconnected-fix
  • v0.10.0
  • v0.11.0
  • v0.5.0
  • v0.6.0
  • v0.6.1
  • v0.6.2
  • v0.7.0
  • v0.7.1
  • v0.7.3
  • v0.8.0
  • v0.9.0
  • xcorr

pending completion
45

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travis-ci-com

Chiranth Siddappa
Manual merge to add other example

284 of 376 relevant lines covered (75.53%)

1.51 hits per line

Relevant lines Covered
Build:
Build:
376 RELEVANT LINES 284 COVERED LINES
1.51 HITS PER LINE
Source Files on sig-gen
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
45 sig-gen Manual merge to add other example push 17 Nov 2018 06:18PM UTC Chiranth Siddappa travis-ci-com pending completion  
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