chiranthsiddappa / caf_verilog
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LAST BUILD BRANCH: prepend-keys
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Chiranth Siddappa 
Removing shifting examples from dot product notebook

382 of 446 relevant lines covered (85.65%)

1.72 hits per line

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446 RELEVANT LINES 382 COVERED LINES
1.72 HITS PER LINE
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
79 dot-prod-pip Removing shifting examples from dot product notebook push Chiranth Siddappa travis-ci-com pending completion  
78 dot-prod-pip Dot product completed push Chiranth Siddappa travis-ci-com pending completion  
70 dot-prod-pip Removing unused variable from testbench push Chiranth Siddappa travis-ci-com pending completion  
69 dot-prod-pip Testing the master tready signal and ending simulation early push Chiranth Siddappa travis-ci-com pending completion  
68 dot-prod-pip Producing the summation push Chiranth Siddappa travis-ci-com pending completion  
67 dot-prod-pip Overriding template dict method with an addition for length counter size push Chiranth Siddappa travis-ci-com pending completion  
58 dot-prod-pip Template ready for usage in testing push Chiranth Siddappa travis-ci-com pending completion  
55 dot-prod-pip Adding source of dot_prod_pip module push Chiranth Siddappa travis-ci-com pending completion  
54 dot-prod-pip Adding instantiation of dot_prod_pip module push Chiranth Siddappa travis-ci-com pending completion  
53 dot-prod-pip New module for shifting signals around push Chiranth Siddappa travis-ci-com pending completion  
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