chiranthsiddappa / caf_verilog
88%
master: 90%

LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH reference_buffer
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Chiranth Siddappa 
Merge branch 'master' into reference_buffer

484 of 548 relevant lines covered (88.32%)

1.77 hits per line

Relevant lines Covered
548 RELEVANT LINES 484 COVERED LINES
1.77 HITS PER LINE
Source Files on reference_buffer
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
112 reference_buffer Merge branch 'master' into reference_buffer push Chiranth Siddappa travis-ci-com pending completion  
111 reference_buffer Adding signal changes for s axi rvalid signal push Chiranth Siddappa travis-ci-com pending completion  
87 reference_buffer Moving bin_num from caf_verilog_base to quantizer push Chiranth Siddappa travis-ci-com pending completion  
86 reference_buffer Specifying tb name in reference buffer jupyter notebook example push Chiranth Siddappa travis-ci-com pending completion  
85 reference_buffer Reference Buffer notebook updated and sample output added push Chiranth Siddappa travis-ci-com pending completion  
84 reference_buffer Refactoring sig_gen for bin_num push Chiranth Siddappa travis-ci-com pending completion  
82 reference_buffer First instantiations of instance and tb modules for reference buffer push Chiranth Siddappa travis-ci-com pending completion  
81 reference_buffer Adding notebook to test reference buffer push Chiranth Siddappa travis-ci-com pending completion  
See All Builds (140)