chiranthsiddappa / caf_verilog
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master: 90%

LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH capture_buffer
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Chiranth Siddappa 
New timings matched with reference_buffer

484 of 548 relevant lines covered (88.32%)

1.77 hits per line

Relevant lines Covered
548 RELEVANT LINES 484 COVERED LINES
1.77 HITS PER LINE
Source Files on capture_buffer
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
115 capture_buffer New timings matched with reference_buffer push Chiranth Siddappa travis-ci-com pending completion  
107 capture_buffer New code cells test and confirm the output push Chiranth Siddappa travis-ci-com pending completion  
106 capture_buffer Doc string for test push Chiranth Siddappa travis-ci-com pending completion  
105 capture_buffer Using readmemb to load data into testbench push Chiranth Siddappa travis-ci-com pending completion  
104 capture_buffer Adding a test for the test file length push Chiranth Siddappa travis-ci-com pending completion  
103 capture_buffer Testbench can be elaborated; input file values ready to be loaded push Chiranth Siddappa travis-ci-com pending completion  
102 capture_buffer Adding a jupyter notebook for generating capture buffer push Chiranth Siddappa travis-ci-com pending completion  
94 capture_buffer Read and Write AXI transaction signals added to module instantiation push Chiranth Siddappa travis-ci-com pending completion  
See All Builds (140)