chiranthsiddappa / caf_verilog
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master: 90%

LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH v0.7.1
branch: v0.7.1
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Chiranth Siddappa 
Bumping version for reference_buffer timing changes

484 of 548 relevant lines covered (88.32%)

1.77 hits per line

Relevant lines Covered
548 RELEVANT LINES 484 COVERED LINES
1.77 HITS PER LINE
Source Files on v0.7.1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

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114 v0.7.1 Bumping version for reference_buffer timing changes push Chiranth Siddappa travis-ci-com pending completion  
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