chiranthsiddappa / caf_verilog
82%
master: 90%

LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
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Files 30
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LAST BUILD ON BRANCH argmax
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Chiranth Siddappa 
Writing out testbench

484 of 590 relevant lines covered (82.03%)

1.64 hits per line

Relevant lines Covered
590 RELEVANT LINES 484 COVERED LINES
1.64 HITS PER LINE
Source Files on argmax
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

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Builds Branch Commit Type Ran Committer Via Coverage
124 argmax Writing out testbench push Chiranth Siddappa travis-ci-com pending completion  
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