chiranthsiddappa / caf_verilog
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master: 90%

LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
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Files 30
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LAST BUILD ON BRANCH caf
branch: caf
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chiranthsiddappa 
Length check test.ˆ

1 of 955 relevant lines covered (0.1%)

0.85 hits per line

Relevant lines Covered
955 RELEVANT LINES 1 COVERED LINES
0.85 HITS PER LINE
Source Files on caf
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
175 caf Length check test.ˆ push chiranthsiddappa travis-ci-com pending completion  
159 caf Adding notebook example changes push Chiranth Siddappa travis-ci-com pending completion  
158 caf Commiting with sizes used in final implementation push Chiranth Siddappa travis-ci-com pending completion  
157 caf Completed handshake on s_axis_tvalid push Chiranth Siddappa travis-ci-com pending completion  
156 caf Able to find peak with no freq shift push Chiranth Siddappa travis-ci-com pending completion  
155 caf almost getting all values out of caf; cpx_multiply needs original bit selection push Chiranth Siddappa travis-ci-com pending completion  
154 caf Removing pipeline register since it's unused now push Chiranth Siddappa travis-ci-com pending completion  
153 caf Adding caf wiring changes for yi and yq push Chiranth Siddappa travis-ci-com pending completion  
152 caf Final changes to make sure handshake deasserts valid and resets the index push Chiranth Siddappa travis-ci-com pending completion  
151 caf tb changes as caf module was being worked on push Chiranth Siddappa travis-ci-com pending completion  
See All Builds (140)