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phanrahan / magma
74%
master: 75%

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Build:
LAST BUILD BRANCH: hwtypes2
DEFAULT BRANCH: master
Repo Added 09 Jul 2018 08:31PM UTC
Files 146
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LAST BUILD ON BRANCH hwtypes2
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  • 1.0.26
  • add-coreir-clock
  • add-coreir-memory
  • add-gold-newlines
  • add-linter
  • add-namespaces-compile-opt
  • add-ports
  • array-concat
  • assignment
  • bfloat-setitem
  • cache_coreir_context
  • cheat-sheet
  • cheatsheet
  • check-unconnected-ports
  • circuit-combinational
  • circuit-refactor
  • comb-unroll-for-loops
  • compile-target
  • coreir-2
  • coreir-conn-metadata
  • coreir-dev
  • coreir-libs-opts
  • coreir-metadata
  • coreir-split-option
  • coreir-tuple
  • coreir-verilog-instance-params
  • custom_env
  • david-ram-tests
  • debug-names
  • declare-interface
  • default-nodebug
  • define-from-verilog-clocks
  • defineCircuitFromGenWrapperFlag
  • dev
  • document-values
  • dynamic-circuit
  • enclosing-env
  • enforce_unique_names
  • external-verilog-modules
  • fix-array-wiring-error
  • fix-bit-vector
  • fix-coreir-backend-state
  • fix-hash
  • fix-imports
  • fix-mantle-regression
  • fix-pytest
  • fix-repr
  • fix-setdefault
  • fix-setup-cfg
  • fix-split-files
  • fix-uniq
  • fix-warning
  • fix-wiring-error-msg
  • fix-zext
  • fix_I_in_rename
  • fix_nested_clocks
  • flat-length
  • flatten
  • flatten-types-decl-coreir-bug
  • from-sv
  • generator
  • generator-exercise
  • global-wire-experiment
  • handle_coreir_generators_or_modules
  • hierarchical
  • hotfix-combination-renamed-ports
  • hotfix-database
  • hotfix-flattened-name
  • hotfix-from-verilog
  • hotfix-fromverilog
  • hotfix-getvalue-nested
  • hotfix-sim-uniquify
  • hotfix-tuple
  • hotfix-uniquify
  • hwtypes
  • hwtypes2
  • if-statements
  • inout
  • instance-name
  • int_vector
  • lassen
  • lassen-bfloat
  • loop-unroll
  • magma-fix-parser
  • magma-uniquify
  • magma-verilog-wrap
  • magma-wrap-verilog
  • master
  • migrate-testing-to-fault
  • mixed-direction-array
  • named-phi
  • new-adt
  • new-circuit-pipeline
  • new-product
  • new-ssa
  • no-bitvec
  • none-wiring-error-msg
  • operator-docs
  • parse-int-verilog
  • pass-namespaces
  • patch-array-call
  • patch-asynreset
  • patch-flattened-name
  • patch-golds-verilogast
  • patch-resetn
  • patch-tuple-name
  • plus
  • pretty-print-types
  • product-cache
  • pyverilog-upgrade
  • refactor-backend
  • refactor-passes
  • refactor-port-renaming
  • remove-definition-method
  • rename-ports
  • repr-hash
  • repr-sort-instances
  • resetn
  • seq-hierarchy
  • seq-sim-test
  • sequential
  • sequential-async-reset
  • sequential-multiple-outputs
  • sequential-rewrite
  • ssa
  • switch-pyverilog
  • synt-to-verilog
  • test-env
  • uniquification-doc
  • uniquification-fix
  • unwire
  • update_install_coreir
  • use-immutable
  • v0.1.1
  • v0.1.10
  • v0.1.11
  • v0.1.14
  • v0.1.15
  • v0.1.16
  • v0.1.17
  • v0.1.18
  • v0.1.19
  • v0.1.2
  • v0.1.20
  • v0.1.3
  • v0.1.4
  • v0.1.5
  • v0.1.6
  • v0.1.7
  • v0.1.8
  • v0.1.9
  • v1.0.0
  • v1.0.1
  • v1.0.10
  • v1.0.11
  • v1.0.13
  • v1.0.19
  • v1.0.20
  • v1.0.21
  • v1.0.22
  • v1.0.23
  • v1.0.24
  • v1.0.25
  • v1.0.3
  • v1.0.6
  • v1.0.7
  • v1.0.8
  • v1.0.9
  • verilog-deps
  • verilog_inline
  • warnings
  • wiring-errors
  • wiring_constants

pending completion
2495

Pull #515

travis-ci

web-flow
Update magma_2_migration_guide.md
Pull Request #515: Hwtypes2

1250 of 1250 new or added lines in 33 files covered. (100.0%)

10140 of 13634 relevant lines covered (74.37%)

0.74 hits per line

Relevant lines Covered
Build:
Build:
13634 RELEVANT LINES 10140 COVERED LINES
0.74 HITS PER LINE
Source Files on master
Detailed source file information is not available for this build.

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
2495 hwtypes2 Update magma_2_migration_guide.md Pull #515 13 Dec 2019 05:43PM UTC web-flow travis-ci pending completion  
2494 hwtypes2 Update magma_2_migration_guide.md push 13 Dec 2019 05:39PM UTC web-flow travis-ci pending completion  
2493 hwtypes2 Merge branch 'master' into hwtypes2 Pull #515 13 Dec 2019 05:19PM UTC web-flow travis-ci pending completion  
2492 hwtypes2 Merge branch 'master' into hwtypes2 push 13 Dec 2019 05:17PM UTC web-flow travis-ci pending completion  
2491 master Merge pull request #516 from phanrahan/fix-uniq Remove unnec. rename in uniq. pass push 13 Dec 2019 05:17PM UTC web-flow travis-ci pending completion  
2490 master Merge pull request #517 from Kuree/add_debug_option Add separate debug option in *_to_verilog functions push 13 Dec 2019 05:15PM UTC web-flow travis-ci pending completion  
2489 add_debug_option move import around Pull #517 13 Dec 2019 02:19AM UTC web-flow travis-ci pending completion  
2487 fix-uniq Handle multiple rename case in uniq. logic Pull #516 13 Dec 2019 12:03AM UTC web-flow travis-ci pending completion  
2486 fix-uniq Handle multiple rename case in uniq. logic push 13 Dec 2019 12:03AM UTC Rajsekhar Setaluri travis-ci pending completion  
2485 fix-uniq Handle multiple rename case in uniq. logic Pull #516 12 Dec 2019 11:52PM UTC web-flow travis-ci pending completion  
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