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phanrahan / magma
73%
master: 75%

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LAST BUILD BRANCH: hwtypes2
DEFAULT BRANCH: master
Repo Added 09 Jul 2018 08:31PM UTC
Files 146
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LAST BUILD ON BRANCH dev
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  • dev
  • 1.0.26
  • add-coreir-clock
  • add-coreir-memory
  • add-gold-newlines
  • add-linter
  • add-namespaces-compile-opt
  • add-ports
  • array-concat
  • assignment
  • bfloat-setitem
  • cache_coreir_context
  • cheat-sheet
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  • check-unconnected-ports
  • circuit-combinational
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  • compile-target
  • coreir-2
  • coreir-conn-metadata
  • coreir-dev
  • coreir-libs-opts
  • coreir-metadata
  • coreir-split-option
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  • custom_env
  • david-ram-tests
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  • declare-interface
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  • define-from-verilog-clocks
  • defineCircuitFromGenWrapperFlag
  • document-values
  • dynamic-circuit
  • enclosing-env
  • enforce_unique_names
  • external-verilog-modules
  • fix-array-wiring-error
  • fix-bit-vector
  • fix-coreir-backend-state
  • fix-hash
  • fix-imports
  • fix-mantle-regression
  • fix-pytest
  • fix-repr
  • fix-setdefault
  • fix-setup-cfg
  • fix-split-files
  • fix-uniq
  • fix-warning
  • fix-wiring-error-msg
  • fix-zext
  • fix_I_in_rename
  • fix_nested_clocks
  • flat-length
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  • from-sv
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  • hierarchical
  • hotfix-combination-renamed-ports
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  • hotfix-sim-uniquify
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  • hwtypes
  • hwtypes2
  • if-statements
  • inout
  • instance-name
  • int_vector
  • lassen
  • lassen-bfloat
  • loop-unroll
  • magma-fix-parser
  • magma-uniquify
  • magma-verilog-wrap
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  • master
  • migrate-testing-to-fault
  • mixed-direction-array
  • named-phi
  • new-adt
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  • no-bitvec
  • none-wiring-error-msg
  • operator-docs
  • parse-int-verilog
  • pass-namespaces
  • patch-array-call
  • patch-asynreset
  • patch-flattened-name
  • patch-golds-verilogast
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  • plus
  • pretty-print-types
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  • unwire
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  • v0.1.1
  • v0.1.10
  • v0.1.11
  • v0.1.14
  • v0.1.15
  • v0.1.16
  • v0.1.17
  • v0.1.18
  • v0.1.19
  • v0.1.2
  • v0.1.20
  • v0.1.3
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  • v1.0.19
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  • v1.0.25
  • v1.0.3
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  • v1.0.9
  • verilog-deps
  • verilog_inline
  • warnings
  • wiring-errors
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pending completion
1796

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travis-ci

web-flow
add parameter and plus to get_value (#399)

`get_value` now works for +, as well as parameters. This lets you have things like `[WIDTH+1:0]` in module port signatures.

4132 of 5665 relevant lines covered (72.94%)

0.73 hits per line

Relevant lines Covered
Build:
Build:
5665 RELEVANT LINES 4132 COVERED LINES
0.73 HITS PER LINE
Source Files on dev
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
1796 dev add parameter and plus to get_value (#399) `get_value` now works for +, as well as parameters. This lets you have things like `[WIDTH+1:0]` in module port signatures. push 23 May 2019 11:51PM UTC web-flow travis-ci pending completion  
1755 dev Merge pull request #394 from phanrahan/fix-setdefault Use setdefault instead of if key not in dict set key push 16 May 2019 07:59PM UTC web-flow travis-ci pending completion  
1749 dev Update docs push 16 May 2019 05:45PM UTC leonardt travis-ci pending completion  
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