• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

phanrahan / magma
75%
master: 75%

Build:
Build:
LAST BUILD BRANCH: hwtypes2
DEFAULT BRANCH: master
Repo Added 09 Jul 2018 08:31PM UTC
Files 146
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

LAST BUILD ON BRANCH fix-pytest
branch: fix-pytest
CHANGE BRANCH
x
Reset
  • fix-pytest
  • 1.0.26
  • add-coreir-clock
  • add-coreir-memory
  • add-gold-newlines
  • add-linter
  • add-namespaces-compile-opt
  • add-ports
  • array-concat
  • assignment
  • bfloat-setitem
  • cache_coreir_context
  • cheat-sheet
  • cheatsheet
  • check-unconnected-ports
  • circuit-combinational
  • circuit-refactor
  • comb-unroll-for-loops
  • compile-target
  • coreir-2
  • coreir-conn-metadata
  • coreir-dev
  • coreir-libs-opts
  • coreir-metadata
  • coreir-split-option
  • coreir-tuple
  • coreir-verilog-instance-params
  • custom_env
  • david-ram-tests
  • debug-names
  • declare-interface
  • default-nodebug
  • define-from-verilog-clocks
  • defineCircuitFromGenWrapperFlag
  • dev
  • document-values
  • dynamic-circuit
  • enclosing-env
  • enforce_unique_names
  • external-verilog-modules
  • fix-array-wiring-error
  • fix-bit-vector
  • fix-coreir-backend-state
  • fix-hash
  • fix-imports
  • fix-mantle-regression
  • fix-repr
  • fix-setdefault
  • fix-setup-cfg
  • fix-split-files
  • fix-uniq
  • fix-warning
  • fix-wiring-error-msg
  • fix-zext
  • fix_I_in_rename
  • fix_nested_clocks
  • flat-length
  • flatten
  • flatten-types-decl-coreir-bug
  • from-sv
  • generator
  • generator-exercise
  • global-wire-experiment
  • handle_coreir_generators_or_modules
  • hierarchical
  • hotfix-combination-renamed-ports
  • hotfix-database
  • hotfix-flattened-name
  • hotfix-from-verilog
  • hotfix-fromverilog
  • hotfix-getvalue-nested
  • hotfix-sim-uniquify
  • hotfix-tuple
  • hotfix-uniquify
  • hwtypes
  • hwtypes2
  • if-statements
  • inout
  • instance-name
  • int_vector
  • lassen
  • lassen-bfloat
  • loop-unroll
  • magma-fix-parser
  • magma-uniquify
  • magma-verilog-wrap
  • magma-wrap-verilog
  • master
  • migrate-testing-to-fault
  • mixed-direction-array
  • named-phi
  • new-adt
  • new-circuit-pipeline
  • new-product
  • new-ssa
  • no-bitvec
  • none-wiring-error-msg
  • operator-docs
  • parse-int-verilog
  • pass-namespaces
  • patch-array-call
  • patch-asynreset
  • patch-flattened-name
  • patch-golds-verilogast
  • patch-resetn
  • patch-tuple-name
  • plus
  • pretty-print-types
  • product-cache
  • pyverilog-upgrade
  • refactor-backend
  • refactor-passes
  • refactor-port-renaming
  • remove-definition-method
  • rename-ports
  • repr-hash
  • repr-sort-instances
  • resetn
  • seq-hierarchy
  • seq-sim-test
  • sequential
  • sequential-async-reset
  • sequential-multiple-outputs
  • sequential-rewrite
  • ssa
  • switch-pyverilog
  • synt-to-verilog
  • test-env
  • uniquification-doc
  • uniquification-fix
  • unwire
  • update_install_coreir
  • use-immutable
  • v0.1.1
  • v0.1.10
  • v0.1.11
  • v0.1.14
  • v0.1.15
  • v0.1.16
  • v0.1.17
  • v0.1.18
  • v0.1.19
  • v0.1.2
  • v0.1.20
  • v0.1.3
  • v0.1.4
  • v0.1.5
  • v0.1.6
  • v0.1.7
  • v0.1.8
  • v0.1.9
  • v1.0.0
  • v1.0.1
  • v1.0.10
  • v1.0.11
  • v1.0.13
  • v1.0.19
  • v1.0.20
  • v1.0.21
  • v1.0.22
  • v1.0.23
  • v1.0.24
  • v1.0.25
  • v1.0.3
  • v1.0.6
  • v1.0.7
  • v1.0.8
  • v1.0.9
  • verilog-deps
  • verilog_inline
  • warnings
  • wiring-errors
  • wiring_constants

pending completion
2439

push

travis-ci

Rajsekhar Setaluri
[Issue #511] Simplify style-check flow

Moved the pycodestyle out of the default pytest flow. Now devs must
invoke pycodestyle explicitly to run style checks. Travis still runs
these checks, but they are invoked directly from .travis.yml rather than
through pytest.

9780 of 13074 relevant lines covered (74.8%)

0.75 hits per line

Relevant lines Covered
Build:
Build:
13074 RELEVANT LINES 9780 COVERED LINES
0.75 HITS PER LINE
Source Files on fix-pytest
Detailed source file information is not available for this build.

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
2439 fix-pytest [Issue #511] Simplify style-check flow Moved the pycodestyle out of the default pytest flow. Now devs must invoke pycodestyle explicitly to run style checks. Travis still runs these checks, but they are invoked directly from .travis.yml rather th... push 10 Dec 2019 10:27PM UTC Rajsekhar Setaluri travis-ci pending completion  
2440 fix-pytest [Issue #511] Simplify style-check flow Moved the pycodestyle out of the default pytest flow. Now devs must invoke pycodestyle explicitly to run style checks. Travis still runs these checks, but they are invoked directly from .travis.yml rather th... Pull #512 10 Dec 2019 10:26PM UTC web-flow travis-ci pending completion  
See All Builds (1176)
  • Repo on GitHub
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc