phanrahan / magma

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master: 75%

LAST BUILD ON BRANCH switch-pyverilog

branch: switch-pyverilog

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• switch-pyverilog
• 1.0.26
• add-coreir-clock
• add-coreir-memory
• add-gold-newlines
• add-linter
• add-namespaces-compile-opt
• add-ports
• array-concat
• assignment
• bfloat-setitem
• cache_coreir_context
• cheat-sheet
• cheatsheet
• check-unconnected-ports
• circuit-combinational
• circuit-refactor
• comb-unroll-for-loops
• compile-target
• coreir-2
• coreir-conn-metadata
• coreir-dev
• coreir-libs-opts
• coreir-metadata
• coreir-split-option
• coreir-tuple
• coreir-verilog-instance-params
• custom_env
• david-ram-tests
• debug-names
• declare-interface
• default-nodebug
• define-from-verilog-clocks
• defineCircuitFromGenWrapperFlag
• dev
• document-values
• dynamic-circuit
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• enforce_unique_names
• external-verilog-modules
• fix-array-wiring-error
• fix-bit-vector
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• fix-hash
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• fix-mantle-regression
• fix-pytest
• fix-repr
• fix-setdefault
• fix-setup-cfg
• fix-split-files
• fix-uniq
• fix-warning
• fix-wiring-error-msg
• fix-zext
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• fix_nested_clocks
• flat-length
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• flatten-types-decl-coreir-bug
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• hierarchical
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• v1.0.8
• v1.0.9
• verilog-deps
• verilog_inline
• warnings
• wiring-errors
• wiring_constants

Build # 1654

Build Type

push

travis-ci

Committed by web-flow

Commit Message

Merge branch 'master' into switch-pyverilog

Run Details

4045 of 5555 relevant lines covered (72.82%)

0.73 hits per line