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LAST BUILD ON BRANCH fix_nested_clocks

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• fix_nested_clocks
• 1.0.26
• add-coreir-clock
• add-coreir-memory
• add-gold-newlines
• add-linter
• add-namespaces-compile-opt
• add-ports
• array-concat
• assignment
• bfloat-setitem
• cache_coreir_context
• cheat-sheet
• cheatsheet
• check-unconnected-ports
• circuit-combinational
• circuit-refactor
• comb-unroll-for-loops
• compile-target
• coreir-2
• coreir-conn-metadata
• coreir-dev
• coreir-libs-opts
• coreir-metadata
• coreir-split-option
• coreir-tuple
• coreir-verilog-instance-params
• custom_env
• david-ram-tests
• debug-names
• declare-interface
• default-nodebug
• define-from-verilog-clocks
• defineCircuitFromGenWrapperFlag
• dev
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• dynamic-circuit
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• fix-array-wiring-error
• fix-bit-vector
• fix-coreir-backend-state
• fix-hash
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• fix-mantle-regression
• fix-pytest
• fix-repr
• fix-setdefault
• fix-setup-cfg
• fix-split-files
• fix-uniq
• fix-warning
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• fix-zext
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• master
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• operator-docs
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• verilog-deps
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Build # 881

Build Type

push

travis-ci

Committed by David-Durst

Commit Message

added test for nested clocks

Run Details

3160 of 4512 relevant lines covered (70.04%)

0.7 hits per line