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phanrahan / magma
73%
master: 75%

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Build:
LAST BUILD BRANCH: hwtypes2
DEFAULT BRANCH: master
Repo Added 09 Jul 2018 08:31PM UTC
Files 146
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LAST BUILD ON BRANCH ssa
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  • ssa
  • 1.0.26
  • add-coreir-clock
  • add-coreir-memory
  • add-gold-newlines
  • add-linter
  • add-namespaces-compile-opt
  • add-ports
  • array-concat
  • assignment
  • bfloat-setitem
  • cache_coreir_context
  • cheat-sheet
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  • check-unconnected-ports
  • circuit-combinational
  • circuit-refactor
  • comb-unroll-for-loops
  • compile-target
  • coreir-2
  • coreir-conn-metadata
  • coreir-dev
  • coreir-libs-opts
  • coreir-metadata
  • coreir-split-option
  • coreir-tuple
  • coreir-verilog-instance-params
  • custom_env
  • david-ram-tests
  • debug-names
  • declare-interface
  • default-nodebug
  • define-from-verilog-clocks
  • defineCircuitFromGenWrapperFlag
  • dev
  • document-values
  • dynamic-circuit
  • enclosing-env
  • enforce_unique_names
  • external-verilog-modules
  • fix-array-wiring-error
  • fix-bit-vector
  • fix-coreir-backend-state
  • fix-hash
  • fix-imports
  • fix-mantle-regression
  • fix-pytest
  • fix-repr
  • fix-setdefault
  • fix-setup-cfg
  • fix-split-files
  • fix-uniq
  • fix-warning
  • fix-wiring-error-msg
  • fix-zext
  • fix_I_in_rename
  • fix_nested_clocks
  • flat-length
  • flatten
  • flatten-types-decl-coreir-bug
  • from-sv
  • generator
  • generator-exercise
  • global-wire-experiment
  • handle_coreir_generators_or_modules
  • hierarchical
  • hotfix-combination-renamed-ports
  • hotfix-database
  • hotfix-flattened-name
  • hotfix-from-verilog
  • hotfix-fromverilog
  • hotfix-getvalue-nested
  • hotfix-sim-uniquify
  • hotfix-tuple
  • hotfix-uniquify
  • hwtypes
  • hwtypes2
  • if-statements
  • inout
  • instance-name
  • int_vector
  • lassen
  • lassen-bfloat
  • loop-unroll
  • magma-fix-parser
  • magma-uniquify
  • magma-verilog-wrap
  • magma-wrap-verilog
  • master
  • migrate-testing-to-fault
  • mixed-direction-array
  • named-phi
  • new-adt
  • new-circuit-pipeline
  • new-product
  • new-ssa
  • no-bitvec
  • none-wiring-error-msg
  • operator-docs
  • parse-int-verilog
  • pass-namespaces
  • patch-array-call
  • patch-asynreset
  • patch-flattened-name
  • patch-golds-verilogast
  • patch-resetn
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  • plus
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  • product-cache
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  • refactor-backend
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  • repr-hash
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  • resetn
  • seq-hierarchy
  • seq-sim-test
  • sequential
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  • sequential-rewrite
  • switch-pyverilog
  • synt-to-verilog
  • test-env
  • uniquification-doc
  • uniquification-fix
  • unwire
  • update_install_coreir
  • use-immutable
  • v0.1.1
  • v0.1.10
  • v0.1.11
  • v0.1.14
  • v0.1.15
  • v0.1.16
  • v0.1.17
  • v0.1.18
  • v0.1.19
  • v0.1.2
  • v0.1.20
  • v0.1.3
  • v0.1.4
  • v0.1.5
  • v0.1.6
  • v0.1.7
  • v0.1.8
  • v0.1.9
  • v1.0.0
  • v1.0.1
  • v1.0.10
  • v1.0.11
  • v1.0.13
  • v1.0.19
  • v1.0.20
  • v1.0.21
  • v1.0.22
  • v1.0.23
  • v1.0.24
  • v1.0.25
  • v1.0.3
  • v1.0.6
  • v1.0.7
  • v1.0.8
  • v1.0.9
  • verilog-deps
  • verilog_inline
  • warnings
  • wiring-errors
  • wiring_constants

pending completion
1339

Pull #324

travis-ci

web-flow
rename inputs and see what breaks
Pull Request #324: Initialize ssa decorator

122 of 122 new or added lines in 4 files covered. (100.0%)

3607 of 4971 relevant lines covered (72.56%)

0.73 hits per line

Relevant lines Covered
Build:
Build:
4971 RELEVANT LINES 3607 COVERED LINES
0.73 HITS PER LINE
Source Files on ssa
Detailed source file information is not available for this build.

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
1339 ssa rename inputs and see what breaks Pull #324 09 Jan 2019 08:22PM UTC web-flow travis-ci pending completion  
1338 ssa rename inputs and see what breaks push 09 Jan 2019 08:22PM UTC THofstee travis-ci pending completion  
1322 ssa Fix issue with combinational Pull #324 14 Dec 2018 09:49PM UTC web-flow travis-ci pending completion  
1321 ssa Fix issue with combinational push 14 Dec 2018 09:33PM UTC leonardt travis-ci pending completion  
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