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phanrahan / magma
73%
master: 75%

Build:
Build:
LAST BUILD BRANCH: hwtypes2
DEFAULT BRANCH: master
Repo Added 09 Jul 2018 08:31PM UTC
Files 146
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LAST BUILD ON BRANCH dynamic-circuit
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  • dynamic-circuit
  • 1.0.26
  • add-coreir-clock
  • add-coreir-memory
  • add-gold-newlines
  • add-linter
  • add-namespaces-compile-opt
  • add-ports
  • array-concat
  • assignment
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  • cheat-sheet
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  • check-unconnected-ports
  • circuit-combinational
  • circuit-refactor
  • comb-unroll-for-loops
  • compile-target
  • coreir-2
  • coreir-conn-metadata
  • coreir-dev
  • coreir-libs-opts
  • coreir-metadata
  • coreir-split-option
  • coreir-tuple
  • coreir-verilog-instance-params
  • custom_env
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  • debug-names
  • declare-interface
  • default-nodebug
  • define-from-verilog-clocks
  • defineCircuitFromGenWrapperFlag
  • dev
  • document-values
  • enclosing-env
  • enforce_unique_names
  • external-verilog-modules
  • fix-array-wiring-error
  • fix-bit-vector
  • fix-coreir-backend-state
  • fix-hash
  • fix-imports
  • fix-mantle-regression
  • fix-pytest
  • fix-repr
  • fix-setdefault
  • fix-setup-cfg
  • fix-split-files
  • fix-uniq
  • fix-warning
  • fix-wiring-error-msg
  • fix-zext
  • fix_I_in_rename
  • fix_nested_clocks
  • flat-length
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  • from-sv
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  • hierarchical
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  • hwtypes
  • hwtypes2
  • if-statements
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  • instance-name
  • int_vector
  • lassen
  • lassen-bfloat
  • loop-unroll
  • magma-fix-parser
  • magma-uniquify
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  • master
  • migrate-testing-to-fault
  • mixed-direction-array
  • named-phi
  • new-adt
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  • new-product
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  • no-bitvec
  • none-wiring-error-msg
  • operator-docs
  • parse-int-verilog
  • pass-namespaces
  • patch-array-call
  • patch-asynreset
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  • plus
  • pretty-print-types
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  • refactor-backend
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  • v0.1.1
  • v0.1.10
  • v0.1.11
  • v0.1.14
  • v0.1.15
  • v0.1.16
  • v0.1.17
  • v0.1.18
  • v0.1.19
  • v0.1.2
  • v0.1.20
  • v0.1.3
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  • v0.1.5
  • v0.1.6
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  • v0.1.8
  • v0.1.9
  • v1.0.0
  • v1.0.1
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  • v1.0.11
  • v1.0.13
  • v1.0.19
  • v1.0.20
  • v1.0.21
  • v1.0.22
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  • v1.0.24
  • v1.0.25
  • v1.0.3
  • v1.0.6
  • v1.0.7
  • v1.0.8
  • v1.0.9
  • verilog-deps
  • verilog_inline
  • warnings
  • wiring-errors
  • wiring_constants

pending completion
1535

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travis-ci

rsetaluri
Push definition on stack during clock wiring pass

3872 of 5269 relevant lines covered (73.49%)

0.73 hits per line

Relevant lines Covered
Build:
Build:
5269 RELEVANT LINES 3872 COVERED LINES
0.73 HITS PER LINE
Source Files on dynamic-circuit
Detailed source file information is not available for this build.

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
1535 dynamic-circuit Push definition on stack during clock wiring pass push 01 Mar 2019 08:21PM UTC rsetaluri travis-ci pending completion  
1534 dynamic-circuit Refactor currentDefinition into own file push 28 Feb 2019 09:55PM UTC rsetaluri travis-ci pending completion  
1530 dynamic-circuit Add ports to all instances when adding to a defn push 28 Feb 2019 07:29PM UTC rsetaluri travis-ci pending completion  
1526 dynamic-circuit Keep track of all instances of a definition We do this by keeping a set of all instances for a definition in the class-level (static) member "self_instances". One question is whether we should only keep track of those instances which are actuall... push 28 Feb 2019 07:05PM UTC rsetaluri travis-ci pending completion  
1513 dynamic-circuit Move interface logic to interface.py push 22 Feb 2019 07:28PM UTC rsetaluri travis-ci pending completion  
1447 dynamic-circuit Move interface logic to interface.py push 08 Feb 2019 10:43PM UTC rsetaluri travis-ci pending completion  
1440 dynamic-circuit Add method to add ports to circuit TODO: add tests for this feature push 08 Feb 2019 07:39PM UTC rsetaluri travis-ci pending completion  
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