phanrahan / magma

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LAST BUILD ON BRANCH compile-target

branch: compile-target

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• compile-target
• 1.0.26
• add-coreir-clock
• add-coreir-memory
• add-gold-newlines
• add-linter
• add-namespaces-compile-opt
• add-ports
• array-concat
• assignment
• bfloat-setitem
• cache_coreir_context
• cheat-sheet
• cheatsheet
• check-unconnected-ports
• circuit-combinational
• circuit-refactor
• comb-unroll-for-loops
• coreir-2
• coreir-conn-metadata
• coreir-dev
• coreir-libs-opts
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• coreir-split-option
• coreir-tuple
• coreir-verilog-instance-params
• custom_env
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• debug-names
• declare-interface
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• define-from-verilog-clocks
• defineCircuitFromGenWrapperFlag
• dev
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• fix-array-wiring-error
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• fix-hash
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• fix-pytest
• fix-repr
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• fix-setup-cfg
• fix-split-files
• fix-uniq
• fix-warning
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• fix-zext
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• fix_nested_clocks
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• magma-fix-parser
• magma-uniquify
• magma-verilog-wrap
• magma-wrap-verilog
• master
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• mixed-direction-array
• named-phi
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• operator-docs
• parse-int-verilog
• pass-namespaces
• patch-array-call
• patch-asynreset
• patch-flattened-name
• patch-golds-verilogast
• patch-resetn
• patch-tuple-name
• plus
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• repr-hash
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• sequential
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• sequential-rewrite
• ssa
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• test-env
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• uniquification-fix
• unwire
• update_install_coreir
• use-immutable
• v0.1.1
• v0.1.10
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• v0.1.14
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• v0.1.16
• v0.1.17
• v0.1.18
• v0.1.19
• v0.1.2
• v0.1.20
• v0.1.3
• v0.1.4
• v0.1.5
• v0.1.6
• v0.1.7
• v0.1.8
• v0.1.9
• v1.0.0
• v1.0.1
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• v1.0.11
• v1.0.13
• v1.0.19
• v1.0.20
• v1.0.21
• v1.0.22
• v1.0.23
• v1.0.24
• v1.0.25
• v1.0.3
• v1.0.6
• v1.0.7
• v1.0.8
• v1.0.9
• verilog-deps
• verilog_inline
• warnings
• wiring-errors
• wiring_constants

Build # 2228

Build Type

Pull #475

travis-ci

Committed by web-flow

Commit Message

Change default compile target to coreir-verilog

Pull Request Pull Request #475: Change default compile target to coreir-verilog

Run Details

1 of 1 new or added line in 1 file covered. (100.0%)

8830 of 11846 relevant lines covered (74.54%)

0.75 hits per line