phanrahan / magma

74%

master: 75%

LAST BUILD ON BRANCH hotfix-getvalue-nested

branch: hotfix-getvalue-nested

CHANGE BRANCH

x

Reset

• hotfix-getvalue-nested
• 1.0.26
• add-coreir-clock
• add-coreir-memory
• add-gold-newlines
• add-linter
• add-namespaces-compile-opt
• add-ports
• array-concat
• assignment
• bfloat-setitem
• cache_coreir_context
• cheat-sheet
• cheatsheet
• check-unconnected-ports
• circuit-combinational
• circuit-refactor
• comb-unroll-for-loops
• compile-target
• coreir-2
• coreir-conn-metadata
• coreir-dev
• coreir-libs-opts
• coreir-metadata
• coreir-split-option
• coreir-tuple
• coreir-verilog-instance-params
• custom_env
• david-ram-tests
• debug-names
• declare-interface
• default-nodebug
• define-from-verilog-clocks
• defineCircuitFromGenWrapperFlag
• dev
• document-values
• dynamic-circuit
• enclosing-env
• enforce_unique_names
• external-verilog-modules
• fix-array-wiring-error
• fix-bit-vector
• fix-coreir-backend-state
• fix-hash
• fix-imports
• fix-mantle-regression
• fix-pytest
• fix-repr
• fix-setdefault
• fix-setup-cfg
• fix-split-files
• fix-uniq
• fix-warning
• fix-wiring-error-msg
• fix-zext
• fix_I_in_rename
• fix_nested_clocks
• flat-length
• flatten
• flatten-types-decl-coreir-bug
• from-sv
• generator
• generator-exercise
• global-wire-experiment
• handle_coreir_generators_or_modules
• hierarchical
• hotfix-combination-renamed-ports
• hotfix-database
• hotfix-flattened-name
• hotfix-from-verilog
• hotfix-fromverilog
• hotfix-sim-uniquify
• hotfix-tuple
• hotfix-uniquify
• hwtypes
• hwtypes2
• if-statements
• inout
• instance-name
• int_vector
• lassen
• lassen-bfloat
• loop-unroll
• magma-fix-parser
• magma-uniquify
• magma-verilog-wrap
• magma-wrap-verilog
• master
• migrate-testing-to-fault
• mixed-direction-array
• named-phi
• new-adt
• new-circuit-pipeline
• new-product
• new-ssa
• no-bitvec
• none-wiring-error-msg
• operator-docs
• parse-int-verilog
• pass-namespaces
• patch-array-call
• patch-asynreset
• patch-flattened-name
• patch-golds-verilogast
• patch-resetn
• patch-tuple-name
• plus
• pretty-print-types
• product-cache
• pyverilog-upgrade
• refactor-backend
• refactor-passes
• refactor-port-renaming
• remove-definition-method
• rename-ports
• repr-hash
• repr-sort-instances
• resetn
• seq-hierarchy
• seq-sim-test
• sequential
• sequential-async-reset
• sequential-multiple-outputs
• sequential-rewrite
• ssa
• switch-pyverilog
• synt-to-verilog
• test-env
• uniquification-doc
• uniquification-fix
• unwire
• update_install_coreir
• use-immutable
• v0.1.1
• v0.1.10
• v0.1.11
• v0.1.14
• v0.1.15
• v0.1.16
• v0.1.17
• v0.1.18
• v0.1.19
• v0.1.2
• v0.1.20
• v0.1.3
• v0.1.4
• v0.1.5
• v0.1.6
• v0.1.7
• v0.1.8
• v0.1.9
• v1.0.0
• v1.0.1
• v1.0.10
• v1.0.11
• v1.0.13
• v1.0.19
• v1.0.20
• v1.0.21
• v1.0.22
• v1.0.23
• v1.0.24
• v1.0.25
• v1.0.3
• v1.0.6
• v1.0.7
• v1.0.8
• v1.0.9
• verilog-deps
• verilog_inline
• warnings
• wiring-errors
• wiring_constants

Build # 1866

Build Type

Pull #416

travis-ci

Committed by web-flow

Commit Message

Relax condition for rewriting select path for nested type

Before the logic was only rewriting the select path when an array or
tuple object was reference from an Array or Tuple. This relaxes it
to always rewrite the select path when any object is referenced from
an Array or Tuple.

In the case of https://github.com/phanrahan/magma/issues/415, a Bit was
being selected from a Tuple, but was not rewritten because it failed
the condition:

    isinstance(arrOrTuple, ArrayType) or \
    isinstance(arrOrTuple, TupleType)

However, regardless of the type of the child object that is being
selected from the tuple/array, we should be rewriting the select path
to flatten out the tuple/array

Pull Request Pull Request #416: Relax condition for rewriting select path for nested type

Run Details

2 of 2 new or added lines in 1 file covered. (100.0%)

4233 of 5705 relevant lines covered (74.2%)

0.74 hits per line