leonardt
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silica
74%
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Repo Added
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Files
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master
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travis-ci
2231 of 3026 relevant lines covered (73.73%)
0.74 hits per line
Relevant lines Covered
3026
RELEVANT LINES
2231
COVERED LINES
0.74
HITS PER LINE
Source Files on master
| Coverage | ∆ | File | Lines | Relevant | Covered | Missed | Hits/Line |
|---|
Recent builds
| Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
|---|---|---|---|---|---|---|---|
| 469 | master | Rework reset logic synthesis | push |  leonardt |
travis-ci | pending completion | |
| 468 | master | Update fault req | push | leonardt |
travis-ci | pending completion | |
| 465 | master | Add reset logic and jtag | push | leonardt |
travis-ci | pending completion | |
| 464 | master | Add note about synchronous reset | push | leonardt |
travis-ci | pending completion | |
| 463 | master | SDRAM passes test! | push | leonardt |
travis-ci | pending completion | |
| 462 | master | Init reg logic | push | leonardt |
travis-ci | pending completion | |
| 461 | master | Test cmd and fix output bug | push | leonardt |
travis-ci | pending completion | |
| 460 | master | Basic sdram test | push | leonardt |
travis-ci | pending completion | |
| 459 | master | Use ifelse pattern | push | leonardt |
travis-ci | pending completion | |
| 458 | master | Fix cfg bug | push | leonardt |
travis-ci | pending completion |