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leonardt / silica
68%
master: 74%

Build:
Build:
LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
Repo Added 03 Oct 2018 09:08PM UTC
Files 36
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LAST BUILD ON BRANCH verilog_fix
branch: verilog_fix
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pending completion
337

Pull #18

travis-ci

web-flow
couple of minor fixes. send_cnt was not being initialized in one of them
Pull Request #18: Verilog fix

1662 of 2427 relevant lines covered (68.48%)

0.68 hits per line

Relevant lines Covered
Build:
Build:
2427 RELEVANT LINES 1662 COVERED LINES
0.68 HITS PER LINE
Source Files on verilog_fix
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
337 verilog_fix couple of minor fixes. send_cnt was not being initialized in one of them Pull #18 09 Nov 2018 12:05AM UTC web-flow travis-ci pending completion  
336 verilog_fix couple of minor fixes. send_cnt was not being initialized in one of them push 09 Nov 2018 12:03AM UTC rdaly525 travis-ci pending completion  
335 verilog_fix cleaned up verilog to explicitly indicate constant bitwidths. used single bit when adding 1. push 08 Nov 2018 11:46PM UTC rdaly525 travis-ci pending completion  
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