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leonardt / silica
57%
master: 74%

Build:
Build:
LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
Repo Added 03 Oct 2018 09:08PM UTC
Files 36
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LAST BUILD ON BRANCH SSA
branch: SSA
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  • SSA
  • ac_channel
  • channel-macros
  • desugar
  • fun-sig-master
  • function
  • jtag2
  • master
  • new-ssa
  • optimize
  • patch-ssa
  • path-based-synthesis
  • tap
  • tap_verilog
  • uart-shift
  • verilog-backend
  • verilog_fix
  • wire-syntax
  • xmodem

pending completion
162

Pull #7

travis-ci

web-flow
remove doctest
Pull Request #7: Init SSA based verilog synthesis

366 of 366 new or added lines in 8 files covered. (100.0%)

1241 of 2190 relevant lines covered (56.67%)

0.57 hits per line

Relevant lines Covered
Build:
Build:
2190 RELEVANT LINES 1241 COVERED LINES
0.57 HITS PER LINE
Source Files on SSA
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
162 SSA remove doctest Pull #7 03 Oct 2018 10:06PM UTC web-flow travis-ci pending completion  
161 SSA remove doctest push 03 Oct 2018 10:06PM UTC leonardt travis-ci pending completion  
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  • Repo on GitHub
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