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leonardt / silica
69%
master: 74%

Build:
Build:
LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
Repo Added 03 Oct 2018 09:08PM UTC
Files 36
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LAST BUILD ON BRANCH uart-shift
branch: uart-shift
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  • uart-shift
  • SSA
  • ac_channel
  • channel-macros
  • desugar
  • fun-sig-master
  • function
  • jtag2
  • master
  • new-ssa
  • optimize
  • patch-ssa
  • path-based-synthesis
  • tap
  • tap_verilog
  • verilog-backend
  • verilog_fix
  • wire-syntax
  • xmodem

pending completion
357

push

travis-ci

leonardt
Add missing .py file

1789 of 2605 relevant lines covered (68.68%)

0.69 hits per line

Relevant lines Covered
Build:
Build:
2605 RELEVANT LINES 1789 COVERED LINES
0.69 HITS PER LINE
Source Files on uart-shift
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
357 uart-shift Add missing .py file push 15 Nov 2018 02:56AM UTC leonardt travis-ci pending completion  
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