leonardt / silica
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master: 74%

LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH verilog-backend
branch: verilog-backend
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THofstee 
remove get_width_str

1273 of 1770 relevant lines covered (71.92%)

0.72 hits per line

Relevant lines Covered
1770 RELEVANT LINES 1273 COVERED LINES
0.72 HITS PER LINE
Source Files on verilog-backend
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
183 verilog-backend remove get_width_str push THofstee travis-ci pending completion  
184 verilog-backend remove get_width_str Pull #9 web-flow travis-ci pending completion  
182 verilog-backend Merge branch 'master' into verilog-backend Pull #9 web-flow travis-ci pending completion  
179 verilog-backend refactor verilog codegen and remove verilog strings push THofstee travis-ci pending completion  
176 verilog-backend remove strategy 'by-path' push THofstee travis-ci pending completion  
174 verilog-backend remove import * push leonardt travis-ci pending completion  
173 verilog-backend remove import * Pull #8 web-flow travis-ci pending completion  
172 verilog-backend Merge branch 'master' into verilog-backend Pull #8 web-flow travis-ci pending completion  
171 verilog-backend Merge branch 'master' into verilog-backend push leonardt travis-ci pending completion  
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