leonardt / silica
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master: 74%

LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH tap_verilog
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web-flow 
Update requirements.txt

1425 of 1966 relevant lines covered (72.48%)

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1966 RELEVANT LINES 1425 COVERED LINES
0.72 HITS PER LINE
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
256 tap_verilog Update requirements.txt push web-flow travis-ci pending completion  
257 tap_verilog Update requirements.txt Pull #13 web-flow travis-ci pending completion  
241 tap_verilog corrected comments in verilog Pull #13 web-flow travis-ci pending completion  
240 tap_verilog corrected comments in verilog push rdaly525 travis-ci pending completion  
239 tap_verilog added fault to requirements.txt. fixed tap.v to be correct. Created jtagdriver and test push rdaly525 travis-ci pending completion  
229 tap_verilog Merge branch 'master' into tap_verilog push rdaly525 travis-ci pending completion  
228 tap_verilog added untested verilog for a basic tap controller. Passes verilator linting push rdaly525 travis-ci pending completion  
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