leonardt
/
silica
72%
master: 74%
master: 74%
|
Repo Added
|
Files
36
|
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README BADGES
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LAST BUILD ON BRANCH tap_verilog
push
travis-ci
1425 of 1966 relevant lines covered (72.48%)
0.72 hits per line
Relevant lines Covered
1966
RELEVANT LINES
1425
COVERED LINES
0.72
HITS PER LINE
Source Files on tap_verilog
| Coverage | ∆ | File | Lines | Relevant | Covered | Missed | Hits/Line |
|---|
Recent builds
| Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
|---|---|---|---|---|---|---|---|
| 256 | tap_verilog | Update requirements.txt | push |  web-flow |
travis-ci | pending completion | |
| 257 | tap_verilog | Update requirements.txt | Pull #13 | web-flow |
travis-ci | pending completion | |
| 241 | tap_verilog | corrected comments in verilog | Pull #13 | web-flow |
travis-ci | pending completion | |
| 240 | tap_verilog | corrected comments in verilog | push |  rdaly525 |
travis-ci | pending completion | |
| 239 | tap_verilog | added fault to requirements.txt. fixed tap.v to be correct. Created jtagdriver and test | push | rdaly525 |
travis-ci | pending completion | |
| 229 | tap_verilog | Merge branch 'master' into tap_verilog | push | rdaly525 |
travis-ci | pending completion | |
| 228 | tap_verilog | added untested verilog for a basic tap controller. Passes verilator linting | push | rdaly525 |
travis-ci | pending completion |