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LAST BUILD ON BRANCH verilog-const-func-ifgen

branch: verilog-const-func-ifgen

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Build # 24177922095

Build Type

Pull #1483

github

Committed by web-flow

Commit Message

Merge a37a5a426 into bf93ddbf1

Pull Request Pull Request #1483: Verilog: support constant user functions and if-generate elaboration

Coverage Stats

23 of 24 new or added lines in 3 files covered. (95.83%)

76335 of 82635 relevant lines covered (92.38%)

608959.01 hits per line