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LAST BUILD ON BRANCH verilog-gen-case-elseif

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Build # 24135597628

Build Type

Pull #1484

github

Committed by web-flow

Commit Message

Merge 7150ff53c into 0a216e610

Pull Request Pull Request #1484: Verilog: support generate case and else-if constructs

Coverage Stats

43 of 50 new or added lines in 1 file covered. (86.0%)

1 existing line in 1 file now uncovered.

76264 of 82533 relevant lines covered (92.4%)

594850.65 hits per line