nickg / nvc
92%
master: 92%

LAST BUILD BRANCH: issue-1248
DEFAULT BRANCH: master
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Files 103
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coverage: 92.4% (+0.001%) from 92.399%
32343887692

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nickg 
Implement System Verilog sized casts

71 of 77 new or added lines in 5 files covered. (92.21%)

1 existing line in 1 file now uncovered.

80777 of 87421 relevant lines covered (92.4%)

687743.01 hits per line

Relevant lines Covered
87421 RELEVANT LINES 80777 COVERED LINES
687743.01 HITS PER LINE
Source Files on test

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
32343887692 test Implement System Verilog sized casts push nickg github
92.4
32227082669 test Allow getting name of vhpiFuncDeclK and vhpiProcDeclK push nickg github
92.4
32187369880 test Avoid NaNs in Cobertura stats push nickg github
92.4
32056261782 test Fix more instances of missing ident_casecmp push nickg github
92.4
32009049955 test Avoid case-sensitive comparison in elab_ports push nickg github
92.4
31579174546 test Handle block comments in macro definitions push nickg github
92.4
31471222329 test Check for missing port and generics in default binding push nickg github
92.4
31312679142 test Add a zero delay waveform fast path push nickg github
92.4
31286827727 test Fix assertion failures with LLVM 8.0 debug build push nickg github
92.39
31211366930 test Pass null context to Verilog posedge/negedge helpers push nickg github
92.37
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