nickg / nvc
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master: 92%

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coverage: 92.265% (-0.004%) from 92.269%
26395823927

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nickg 
Improve checking for Verilog constant expressions

78 of 87 new or added lines in 5 files covered. (89.66%)

246 existing lines in 8 files now uncovered.

78777 of 85381 relevant lines covered (92.27%)

630338.01 hits per line

Relevant lines Covered
85381 RELEVANT LINES 78777 COVERED LINES
630338.01 HITS PER LINE
Source Files on test

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
26395823927 test Improve checking for Verilog constant expressions push nickg github
92.27
26328771286 test Update for 1.21 release push nickg github
92.27
26328090526 test Fix LLVM test workflow push nickg github
92.27
26276308025 test Handle Verilog divison/mod corner cases push nickg github
92.26
26250093480 test Parse octal escapes in Verilog strings push nickg github
92.25
26211985686 test Recurse to base type in type_constraint_for_field push nickg github
92.24
26211195713 test Recursively process generic packages in elab_map_generic_package push nickg github
92.24
26189081335 test Fix external names referring to nested arrays push nickg github
92.24
26052457493 test Fix mis-optimisation of real subtraction from zero push nickg github
92.23
26021122736 test Add $pow and $clog2 system tasks push nickg github
92.22
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