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nickg / nvc / 24177922095
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 09 Apr 2026 07:35AM UTC
Jobs 1
Files 101
Run time 1min
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09 Apr 2026 07:23AM UTC coverage: 92.376% (+0.004%) from 92.372%
24177922095

Pull #1483

github

web-flow
Merge a37a5a426 into bf93ddbf1
Pull Request #1483: Verilog: support constant user functions and if-generate elaboration

23 of 24 new or added lines in 3 files covered. (95.83%)

76335 of 82635 relevant lines covered (92.38%)

608959.01 hits per line

Uncovered Changes

Lines Coverage ∆ File
1
91.25
0.19% src/elab.c
Jobs
ID Job ID Ran Files Coverage
1 24177922095.1 09 Apr 2026 07:35AM UTC 101
92.38
GitHub Action Run
Source Files on build 24177922095
  • Tree
  • List 101
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • Pull Request #1483
  • PR Base - master (#24161187076)
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