nickg / nvc
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coverage: 92.267%. Remained the same
26533822565

Pull #1513

github

web-flow 
Merge 0e23a5f7c into 97397e72d
Pull Request #1513: Verilog: Support default values on macro functions

6 of 6 new or added lines in 1 file covered. (100.0%)

78956 of 85573 relevant lines covered (92.27%)

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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
26533822565 macrodef Merge 0e23a5f7c into 97397e72d Pull #1513 web-flow github
92.27
26498179540 fix/vhpi-array-record-fields-upstream Merge f6f40aa01 into 97397e72d Pull #1555 web-flow github
92.27
26470279797 master Implement $itor system function push nickg github
92.27
26469207423 master Constant fold replication count in Verilog concatenation (#1551) Completes constant folding introduced in e9e33ba1d by also folding the replication count of a concatenation node. Without this an expression like {(WIDTH + 1){1'b1}}, where WIDTH i... push web-flow github
92.27
26469181143 vlog-fold-concat-replication Merge 84cd59761 into 1e91536d7 Pull #1551 web-flow github
92.27
26469102245 test Implement $itor system function push nickg github
92.27
26441552539 master cLowering for System Verilog $bits push nickg github
92.27
26440966580 vlog-fold-concat-replication Merge 6aa202325 into a5944cd55 Pull #1551 web-flow github
92.26
26421566333 master Lower Verilog ** operator for reals push nickg github
92.27
26421121335 master Expand System Verilog macro string escapes push nickg github
92.27
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