|
Repo Added
|
Files
103
|
Badge
README BADGES
|
push
github
80777 of 87421 relevant lines covered (92.4%)
678792.81 hits per line
| Coverage | ∆ | File | Lines | Relevant | Covered | Missed | Hits/Line |
|---|
| Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
|---|---|---|---|---|---|---|---|
| 32412029710 | master | Add test for issue #1585 | push | github |
92.4 |
||
| 32347086510 | master | Implement System Verilog sized casts Fixes #1640 | push | github |
92.4 |
||
| 32228266171 | master | Allow getting name of vhpiFuncDeclK and vhpiProcDeclK Fixes #1579 | push | github |
92.4 |
||
| 32190571395 | master | Avoid NaNs in Cobertura stats | push | github |
92.4 |
||
| 32057882759 | master | Fix more instances of missing ident_casecmp | push | github |
92.4 |
||
| 31581457648 | master | Handle block comments in macro definitions Fixes #1636 | push | github |
92.4 |
||
| 31472341339 | master | Check for missing port and generics in default binding Fixes #1638 | push | github |
92.4 |
||
| 31314583316 | master | Add a zero delay waveform fast path | push | github |
92.4 |
||
| 31303273647 | master | Fix assertion failures with LLVM 8.0 debug build | push | github |
92.39 |
||
| 31217165561 | master | Pass null context to Verilog posedge/negedge helpers | push | github |
92.37 |