nickg / nvc
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coverage: 92.556% (+0.007%) from 92.549%
18476552328

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nickg 
Parse string variable declarations in modules

3 of 3 new or added lines in 1 file covered. (100.0%)

58 existing lines in 2 files now uncovered.

74514 of 80507 relevant lines covered (92.56%)

446662.89 hits per line

Relevant lines Covered
80507 RELEVANT LINES 74514 COVERED LINES
446662.89 HITS PER LINE
Source Files on master

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
18476552328 master Parse string variable declarations in modules push nickg github
92.56
18428170938 master Better handling of System Verilog nulls push nickg github
92.55
18400212175 master Remove the precompile elaboration mode push nickg github
92.55
18389684953 master Allow separate data type declaration for task/function ports Fixes #1303 push nickg github
92.77
18358391634 master Fix handling of records in lower_constrain_port Fixes #1317 push nickg github
92.77
18326250897 master Handle record element constraints in get_subtype_for Fixes #1318 push nickg github
92.78
18260570527 master System function $clog2 is constant. Fixes #1312 push nickg github
92.77
18249040983 master Improve type checking for Verilog binary operators push nickg github
92.74
18243832564 master Parse more class and method syntax push nickg github
92.73
18242802251 master Fix required argument calculation for subprograms with mode view Fixes #1308 push nickg github
92.72
See All Builds (3709)