leonardt / verilogAST-cpp

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• if
• master
• parameters
• const-expr
• always
• parameterized-test
• comment
• module-str-body
• string
• vector-decl
• default-num-tostr
• unique-ptr
• concat
• 0.0.1
• 0.0.2
• 0.0.3
• 0.0.4
• 0.0.5
• 0.0.7
• 0.0.8
• 0.0.9
• 0.0.10
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• 0.0.12
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• 0.0.17
• 0.0.18
• 0.0.23
• 0.0.13
• 0.0.14
• v0.0.19
• 0.0.20
• 0.0.22
• functions
• compare
• logical-binops
• radix-constructor
• disable-escape
• replicate
• enable-escape
• transformer
• inline-assigns
• copy-constructors
• inline-verilog-node
• comment-contents
• slice-expr
• transform-inline-verilog
• hotfix-assign-inliner
• linebreaks
• expr-comment
• order-ports
• inline-wire-blacklist
• add-concat-coalescer-transformer
• attribute
• fix-corier-853
• inline-verilog-symbol-map
• always-codegen-size
• cast-operator
• slice-index
• add-full-install
• default-radix
• blacklist-slice-inline
• add-zext-coalescer-transformer
• inline-slice-id
• nd-vector
• vector-param
• inline-index-then-slice
• nested-index
• fix-inline-slice-logic
• prevent-inline-into-module-instance
• blacklist-module-instance
• fix-inline-logic-multiple-assign
• prevent-inlining-num-literal
• simplify-regex

Build # 499

Build Type

Pull #49

travis-ci-com

Committed by web-flow

Commit Message

Merge a86e88724 into 9a94ff548

Pull Request Pull Request #49: Add support for If statement

Run Details

61 of 61 new or added lines in 4 files covered. (100.0%)

1009 of 1016 relevant lines covered (99.31%)

113.93 hits per line