leonardt / verilogAST-cpp

100%

master: 98%

LAST BUILD ON BRANCH 0.0.18

branch: 0.0.18

CHANGE BRANCH

x

Reset

• 0.0.18
• 0.0.1
• 0.0.10
• 0.0.11
• 0.0.12
• 0.0.13
• 0.0.14
• 0.0.15
• 0.0.16
• 0.0.17
• 0.0.2
• 0.0.20
• 0.0.22
• 0.0.23
• 0.0.3
• 0.0.4
• 0.0.5
• 0.0.7
• 0.0.8
• 0.0.9
• add-concat-coalescer-transformer
• add-full-install
• add-zext-coalescer-transformer
• always
• always-codegen-size
• attribute
• blacklist-module-instance
• blacklist-slice-inline
• cast-operator
• comment
• comment-contents
• compare
• concat
• const-expr
• copy-constructors
• default-num-tostr
• default-radix
• disable-escape
• enable-escape
• expr-comment
• fix-corier-853
• fix-inline-logic-multiple-assign
• fix-inline-slice-logic
• functions
• hotfix-assign-inliner
• if
• inline-assigns
• inline-index-then-slice
• inline-slice-id
• inline-verilog-node
• inline-verilog-symbol-map
• inline-wire-blacklist
• linebreaks
• logical-binops
• master
• module-str-body
• nd-vector
• nested-index
• order-ports
• parameterized-test
• parameters
• prevent-inline-into-module-instance
• prevent-inlining-num-literal
• radix-constructor
• replicate
• simplify-regex
• slice-expr
• slice-index
• string
• transform-inline-verilog
• transformer
• unique-ptr
• v0.0.19
• vector-decl
• vector-param

Build # 188

Build Type

push

travis-ci-com

Committed by leonardt

Commit Message

Explicitly define wire/reg toSTring

Run Details

371 of 371 relevant lines covered (100.0%)

33.27 hits per line