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README BADGES
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Coverage | ∆ | File | Lines | Relevant | Covered | Missed | Hits/Line |
---|---|---|---|---|---|---|---|
92.31 | src/zext_coalescer.cpp | 64 | 26 | 24 | 2 | 13.0 | |
93.75 | include/verilogAST/assign_inliner.hpp | 180 + 32 | 16 + 3 | 15 + 2 | 1 + 1 | 49.0 + 10 | |
95.12 | src/concat_coalescer.cpp | 106 | 41 | 39 | 2 | 93.0 | |
98.62 | include/verilogAST.hpp | 909 + 7 | 217 + 4 | 214 + 4 | 3 | 93.0 + 7 | |
98.73 | src/assign_inliner.cpp | 315 + 40 | 157 + 18 | 155 + 18 | 2 | 180.0 + 16 | |
100.0 | include/verilogAST/zext_coalescer.hpp | 23 | 1 | 1 | 0 | 9.0 | |
100.0 | include/verilogAST/transformer.hpp | 118 | 2 | 2 | 0 | 1769.0 + 554 | |
100.0 | src/transformer.cpp | 473 | 237 | 237 | 0 | 265.0 + 78 | |
100.0 | src/verilogAST.cpp | 528 | 253 | 253 | 0 | 236.0 + 24 | |
100.0 | include/verilogAST/concat_coalescer.hpp | 18 | 0 | 0 | 0 | 0.0 |
Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
---|---|---|---|---|---|---|---|
555 | fix-inline-slice-logic | Merge c036f8103 into eaa5a43b7 | Pull #58 | travis-ci-com | pending completion | ||
554 | fix-inline-slice-logic | Merge pull request #59 from leonardt/blacklist-module-instance Prevent inlining into module instances | push | travis-ci-com | pending completion | ||
540 | fix-inline-slice-logic | Add numeric literal case | push | travis-ci-com | pending completion | ||
541 | fix-inline-slice-logic | Merge 688ccbab4 into eaa5a43b7 | Pull #58 | travis-ci-com | pending completion | ||
536 | fix-inline-slice-logic | Merge 0aa25698a into eaa5a43b7 | Pull #58 | travis-ci-com | pending completion | ||
535 | fix-inline-slice-logic | Fix inline blacklist logic for recursive case Before if we had a module such as: ```verilog module test_module ( input [4:0] i1, input [4:0] i2, output [3:0] o0, output [3:0] o1, output [3:0] o2 ); wire [4:0] x; wire [4:0] y; ... | push | travis-ci-com | pending completion |