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leonardt / verilogAST-cpp
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LAST BUILD BRANCH: simplify-regex
DEFAULT BRANCH: master
Repo Added 02 May 2019 07:52PM UTC
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LAST BUILD ON BRANCH fix-inline-slice-logic
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pending completion
555

Pull #58

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Merge c036f8103 into eaa5a43b7
Pull Request #58: Fix inline blacklist logic for recursive case

33 of 33 new or added lines in 3 files covered. (100.0%)

1113 of 1127 relevant lines covered (98.76%)

158.84 hits per line

Relevant lines Covered
Build:
Build:
1127 RELEVANT LINES 1113 COVERED LINES
158.84 HITS PER LINE
Source Files on fix-inline-slice-logic
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  • List 10
  • Changed 6
  • Source Changed 3
  • Coverage Changed 6
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
555 fix-inline-slice-logic Merge c036f8103 into eaa5a43b7 Pull #58 31 Aug 2020 09:46PM UTC web-flow travis-ci-com pending completion  
554 fix-inline-slice-logic Merge pull request #59 from leonardt/blacklist-module-instance Prevent inlining into module instances push 31 Aug 2020 09:46PM UTC web-flow travis-ci-com pending completion  
540 fix-inline-slice-logic Add numeric literal case push 27 Aug 2020 09:09PM UTC leonardt travis-ci-com pending completion  
541 fix-inline-slice-logic Merge 688ccbab4 into eaa5a43b7 Pull #58 27 Aug 2020 09:08PM UTC web-flow travis-ci-com pending completion  
536 fix-inline-slice-logic Merge 0aa25698a into eaa5a43b7 Pull #58 27 Aug 2020 12:37AM UTC web-flow travis-ci-com pending completion  
535 fix-inline-slice-logic Fix inline blacklist logic for recursive case Before if we had a module such as: ```verilog module test_module ( input [4:0] i1, input [4:0] i2, output [3:0] o0, output [3:0] o1, output [3:0] o2 ); wire [4:0] x; wire [4:0] y; ... push 27 Aug 2020 12:36AM UTC leonardt travis-ci-com pending completion  
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