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Coverage | ∆ | File | Lines | Relevant | Covered | Missed | Hits/Line |
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Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
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555 | fix-inline-slice-logic | Merge c036f8103 into eaa5a43b7 | Pull #58 | web-flow | travis-ci-com | pending completion | |
554 | fix-inline-slice-logic | Merge pull request #59 from leonardt/blacklist-module-instance Prevent inlining into module instances | push | web-flow | travis-ci-com | pending completion | |
540 | fix-inline-slice-logic | Add numeric literal case | push | leonardt | travis-ci-com | pending completion | |
541 | fix-inline-slice-logic | Merge 688ccbab4 into eaa5a43b7 | Pull #58 | web-flow | travis-ci-com | pending completion | |
536 | fix-inline-slice-logic | Merge 0aa25698a into eaa5a43b7 | Pull #58 | web-flow | travis-ci-com | pending completion | |
535 | fix-inline-slice-logic | Fix inline blacklist logic for recursive case Before if we had a module such as: ```verilog module test_module ( input [4:0] i1, input [4:0] i2, output [3:0] o0, output [3:0] o1, output [3:0] o2 ); wire [4:0] x; wire [4:0] y; ... | push | leonardt | travis-ci-com | pending completion |