nickg / nvc / 16033201661

Builds Branch Commit Type Ran Committer Via Coverage
16033201661 master Handle non-constant bit selects push nickg github
92.26
16033053799 test Handle non-constant bit selects push nickg github
92.26
16021465245 master Lower Verilog pre-increment and bit-select in sensitivity list push nickg github
92.28
16021134934 test Lower Verilog pre-increment and bit-select in sensitivity list push nickg github
92.27
16020164833 test Skip over Verilog attributes while parsing push nickg github
92.27
16010315275 initialfixup Merge 16fdd6bc1 into a6bb8a596 Pull #1228 web-flow github
92.27
16007625582 master Map VHDL generics to Verilog parameters push nickg github
92.26
16006985729 test Map VHDL generics to Verilog parameters push nickg github
92.26
15981753990 master Fix unused function warning in debug build without capstone push nickg github
92.25
15981464653 master Allow parsing empty verilog port connection (#1226) push web-flow github
92.25
15981422681 test Fix unused function warning in debug build without capstone push nickg github
92.25
15981349306 parse-vlog-empty-port Merge e6f5be00d into cb9ee8a39 Pull #1226 web-flow github
92.25
15973638278 parse-vlog-empty-port Merge 1eec45799 into cb9ee8a39 Pull #1226 web-flow github
92.25
15958145723 master Allow referencing Verilog data types by name push nickg github
92.25
15957592848 master Parse fork/join and automatic functions push nickg github
92.24