nickg / nvc / 16006985729
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.26% (+0.009%) from 92.251%
16006985729

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github

nickg 
Map VHDL generics to Verilog parameters

283 of 313 new or added lines in 8 files covered. (90.42%)

43 existing lines in 5 files now uncovered.

70636 of 76562 relevant lines covered (92.26%)

561717.81 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
87.82
 -0.15% src/vlog/vlog-dump.c
5
94.97
 0.17% src/elab.c
6
75.56
 -9.06% src/vlog/vlog-util.c
7
83.33
 -0.76% src/vlog/vlog-simp.c
11
93.12
 -5.28% src/vlog/vlog-trans.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
94.97
 0.17% src/elab.c
1
95.6
 -0.1% src/vlog/vlog-lower.c
1
93.12
 -5.28% src/vlog/vlog-trans.c
13
94.13
 3.08% src/ident.c
27
95.72
 0.0% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 16006985729.1 98
92.26
 GitHub Action Run
Source Files on build 16006985729