nickg / nvc / 16021134934
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.273% (+0.004%) from 92.269%
16021134934

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github

nickg 
Lower Verilog pre-increment and bit-select in sensitivity list

52 of 56 new or added lines in 2 files covered. (92.86%)

1 existing line in 1 file now uncovered.

70690 of 76610 relevant lines covered (92.27%)

562009.36 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
85.58
 -0.55% src/vpi/vpi-model.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
96.02
 0.41% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 16021134934.1 98
92.27
 GitHub Action Run
Source Files on build 16021134934