nickg / nvc / 8807639843
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 1min
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Rst
coverage: 91.681% (+0.003%) from 91.678%
8807639843

push

github

nickg 
Verilog "forever" loops

26 of 26 new or added lines in 4 files covered. (100.0%)

8 existing lines in 2 files now uncovered.

53561 of 58421 relevant lines covered (91.68%)

656799.98 hits per line

Jobs
ID Job ID Ran Files Coverage
1 8807639843.1 0
91.68
 GitHub Action Run
Source Files on build 8807639843
Detailed source file information is not available for this build.