nickg / nvc / 23163104024 / 1
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
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Run time 6s
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coverage: 92.479% (-0.003%) from 92.482%
23163104024.1

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nickg 
Correct size and sign extension rules for Verilog case statement

77857 of 84189 relevant lines covered (92.48%)

435065.83 hits per line

Source Files on job 23163104024.1