nickg / nvc / 23163104024
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 102
Run time 1min
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Rst
coverage: 92.479% (-0.003%) from 92.482%
23163104024

push

github

nickg 
Correct size and sign extension rules for Verilog case statement

83 of 87 new or added lines in 4 files covered. (95.4%)

8 existing lines in 4 files now uncovered.

77857 of 84189 relevant lines covered (92.48%)

435065.83 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
93.34
 0.0% src/jit/jit-core.c
3
97.8
 -0.08% src/jit/jit-irgen.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.3
 -0.14% src/jit/jit-interp.c
2
97.73
 -0.11% src/mir/mir-node.c
2
97.11
 -0.36% src/mir/mir-optim.c
3
92.87
 0.17% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 23163104024.1 102
92.48
 GitHub Action Run
Source Files on build 23163104024