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nickg / nvc / 23185851492 / 1
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 17 Mar 2026 08:57AM UTC
Files 102
Run time 4s
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17 Mar 2026 08:47AM UTC coverage: 92.484% (+0.003%) from 92.481%
23185851492.1

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Correct size and sign extension rules for Verilog case statement

77868 of 84196 relevant lines covered (92.48%)

426660.67 hits per line

Source Files on job 23185851492.1
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  • List 102
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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