nickg / nvc / 16918122786 / 1
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
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Files 98
Run time 5s
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coverage: 92.563% (-0.001%) from 92.564%
16918122786.1

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nickg 
Handle real numbers in Verilog delay values

72016 of 77802 relevant lines covered (92.56%)

551895.86 hits per line

Source Files on job 16918122786.1