nickg / nvc / 16918122786
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.563% (-0.001%) from 92.564%
16918122786

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github

nickg 
Handle real numbers in Verilog delay values

44 of 45 new or added lines in 2 files covered. (97.78%)

2 existing lines in 2 files now uncovered.

72016 of 77802 relevant lines covered (92.56%)

551895.86 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.28
 -0.01% src/vlog/vlog-parse.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.98
 -0.14% src/jit/jit-interp.c
1
96.64
 0.01% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 16918122786.1 98
92.56
 GitHub Action Run
Source Files on build 16918122786