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nickg / nvc / 16891751361 / 1
93%
master: 93%

Build:
DEFAULT BRANCH: master
Ran 11 Aug 2025 09:00PM UTC
Files 98
Run time 4s
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11 Aug 2025 08:35PM UTC coverage: 92.564% (+0.02%) from 92.549%
16891751361.1

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nickg
Lowering for Verilog repeat/while loops

71998 of 77782 relevant lines covered (92.56%)

562416.58 hits per line

Source Files on job 16891751361.1
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  • List 98
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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