nickg / nvc / 16669709596 / 1
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Files 99
Run time 13min
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coverage: 92.402% (-0.005%) from 92.407%
16669709596.1

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github

nickg 
Implement Verilog casex

72189 of 78125 relevant lines covered (92.4%)

559712.3 hits per line

Source Files on job 16669709596.1