nickg / nvc / 16669709596
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 34min
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Rst
coverage: 92.402% (-0.005%) from 92.407%
16669709596

push

github

nickg 
Implement Verilog casex

12 of 21 new or added lines in 4 files covered. (57.14%)

1 existing line in 1 file now uncovered.

72189 of 78125 relevant lines covered (92.4%)

559712.3 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
35.14
 -1.48% src/vpi/vpi-util.c
5
86.21
 -3.88% src/vpi/vpi-systf.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
35.14
 -1.48% src/vpi/vpi-util.c
Jobs
ID Job ID Ran Files Coverage
1 16669709596.1 99
92.4
 GitHub Action Run
Source Files on build 16669709596