SystemRDL / PeakRDL-regblock-vhdl
92%
main: 92%

LAST BUILD BRANCH: v1.1.1.0+vhdl
DEFAULT BRANCH: main
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Files 45
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LAST BUILD ON BRANCH dev/synth-tests
branch: dev/synth-tests
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coverage: 91.962% (+0.006%) from 91.956%
14759925589

Pull #18

github

web-flow 
Merge cdf6d5a10 into 5bd71cba6
Pull Request #18: Port synthesis tests to VHDL

759 of 886 branches covered (85.67%)

Branch coverage included in aggregate %.

2845 of 3033 relevant lines covered (93.8%)

5.63 hits per line

Relevant lines Covered
3033 RELEVANT LINES 2845 COVERED LINES
5.63 HITS PER LINE
Source Files on dev/synth-tests

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
14759925589 dev/synth-tests Merge cdf6d5a10 into 5bd71cba6 Pull #18 web-flow github
91.96
14758908714 dev/synth-tests don't use avalon intf pkg for flattened interface push darsor github
91.96
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