SystemRDL / PeakRDL-regblock-vhdl
92%
main: 92%

LAST BUILD BRANCH: v1.2.0.0+vhdl
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LAST BUILD ON BRANCH v1.2.0.0+vhdl
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coverage: 92.147% (-0.05%) from 92.2%
20557075623

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darsor 
fix read-buffered signed/fixedpoint fields

853 of 990 branches covered (86.16%)

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3066 of 3263 relevant lines covered (93.96%)

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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
20557075623 v1.2.0.0+vhdl fix read-buffered signed/fixedpoint fields push darsor github
92.15
20556698586 main fix read-buffered signed/fixedpoint fields push darsor github
92.15
20546802020 main fix read/write buffering in arrays of regfiles (#31) push darsor github
92.2
20546738636 main fix: correct assignment of single bit read-only storage-less fields (#33) * fix: correct assignment of single bit read-only storage-less fields * add tests for single-bit fields of all types --------- Co-authored-by: Dana Sorensen <dana.r.sore... push web-flow github
92.17
20546638300 fix-ro-singlebit-storageless Merge 6ff7f801c into adcd3ddd9 Pull #33 web-flow github
92.16
20540692408 main include hdl-src files in python wheel (#30) push darsor github
92.18
20513114033 main fix external block address width bug (#29) External regblock addr signals are now always a std_logic_vector, even when the width is 1. push darsor github
92.19
20511038480 main clarified upstream bugfix handling in issue template push web-flow github
92.29
20510926524 main fix jinja syntax error push darsor github
92.29
20478208721 fix-ro-singlebit-storageless Merge 8c766dfb1 into 074320873 Pull #33 web-flow github
92.11
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