SystemRDL / PeakRDL-regblock-vhdl
92%
main: 92%

LAST BUILD BRANCH: v1.1.1.0+vhdl
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LAST BUILD ON BRANCH v1.1.1.0+vhdl
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coverage: 92.141%. Remained the same
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Merge upstream/v1.1.1 into VHDL port

798 of 928 branches covered (85.99%)

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2942 of 3131 relevant lines covered (93.96%)

5.64 hits per line

Relevant lines Covered
3131 RELEVANT LINES 2942 COVERED LINES
5.64 HITS PER LINE
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Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
17847082890 v1.1.1.0+vhdl Merge upstream/v1.1.1 into VHDL port push darsor github
92.14
17831916847 main Merge upstream/v1.1.1 into VHDL port push darsor github
92.14
17799514400 v1.1.0.0+vhdl Merge upstream/v1.1.0 into VHDL port push darsor github
92.14
17799211844 main Merge upstream/v1.1.0 into VHDL port push darsor github
92.14
17799079768 main Merge upstream/v1.1.0 into VHDL port push darsor github
92.14
14764799696 v1.0.0.3+vhdl version 1.0.0.3+vhdl push darsor github
91.96
14764755508 main version 1.0.0.3+vhdl push darsor github
91.96
14764711205 main VHDL updates for readthedocs documentation (#19) * update README * updated readthedocs for VHDL * updated many missed references to systemverilog exporter * added note in quick start about hdl-src/ files push web-flow github
91.96
14764676637 dev/update-docs trigger coveralls build Pull #19 darsor github
91.95
14764452579 dev/update-docs added note in quick start about hdl-src/ files Pull #19 darsor github
91.96
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