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SystemRDL / PeakRDL-regblock-vhdl
92%
main: 92%

Build:
Build:
LAST BUILD BRANCH: v1.2.0.1+vhdl
DEFAULT BRANCH: main
Repo Added 24 Apr 2025 01:14PM UTC
Files 46
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LAST BUILD ON BRANCH v1.2.0.1+vhdl
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  • dev/LGPLv3
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  • v1.2.0.1+vhdl

15 Mar 2026 02:34AM UTC coverage: 92.158% (+0.004%) from 92.154%
23101840265

push

github

darsor
bump version to 1.2.0.1

857 of 994 branches covered (86.22%)

Branch coverage included in aggregate %.

3068 of 3265 relevant lines covered (93.97%)

6.58 hits per line

Relevant lines Covered
Build:
Build:
3265 RELEVANT LINES 3068 COVERED LINES
6.58 HITS PER LINE
Source Files on main
  • Tree
  • List 46
  • Changed 1
  • Source Changed 0
  • Coverage Changed 1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
23101840265 v1.2.0.1+vhdl bump version to 1.2.0.1 push 15 Mar 2026 02:46AM UTC darsor github
92.16
23101693077 main bump version to 1.2.0.1 push 15 Mar 2026 02:35AM UTC darsor github
92.15
22446006992 main Add checklist item for opening an issue before PR push 15 Mar 2026 02:04AM UTC web-flow github
92.15
20557075623 v1.2.0.0+vhdl fix read-buffered signed/fixedpoint fields push 28 Dec 2025 05:20PM UTC darsor github
92.15
20556698586 main fix read-buffered signed/fixedpoint fields push 28 Dec 2025 04:47PM UTC darsor github
92.15
20546802020 main fix read/write buffering in arrays of regfiles (#31) push 28 Dec 2025 01:11AM UTC darsor github
92.2
20546738636 main fix: correct assignment of single bit read-only storage-less fields (#33) * fix: correct assignment of single bit read-only storage-less fields * add tests for single-bit fields of all types --------- Co-authored-by: Dana Sorensen <dana.r.sore... push 28 Dec 2025 01:05AM UTC web-flow github
92.17
20546638300 fix-ro-singlebit-storageless Merge 6ff7f801c into adcd3ddd9 Pull #33 28 Dec 2025 12:55AM UTC web-flow github
92.16
20540692408 main include hdl-src files in python wheel (#30) push 27 Dec 2025 03:10PM UTC darsor github
92.18
20513114033 main fix external block address width bug (#29) External regblock addr signals are now always a std_logic_vector, even when the width is 1. push 26 Dec 2025 12:35AM UTC darsor github
92.19
See All Builds (55)
  • Repo on GitHub
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