SystemRDL / PeakRDL-regblock-vhdl
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coverage: 92.137% (-0.004%) from 92.141%
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Merge upstream/v1.1.1 into VHDL port

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Builds Branch Commit Type Ran Committer Via Coverage
17831916847 main Merge upstream/v1.1.1 into VHDL port push darsor github
92.14
17799211844 main Merge upstream/v1.1.0 into VHDL port push darsor github
92.14
17799079768 main Merge upstream/v1.1.0 into VHDL port push darsor github
92.14
14764755508 main version 1.0.0.3+vhdl push darsor github
91.96
14764711205 main VHDL updates for readthedocs documentation (#19) * update README * updated readthedocs for VHDL * updated many missed references to systemverilog exporter * added note in quick start about hdl-src/ files push web-flow github
91.96
14763659860 main Port synthesis tests to VHDL (#18) * update synthesis test runners for VHDL * don't use avalon intf pkg for flattened interface push web-flow github
91.96
14743637084 main version 1.0.0.2+vhdl (#13, #17) push darsor github
91.96
14740844555 main version 1.0.0.1+vhdl (#15, #17) No functional changes from v1.0.0.0, but now it should deploy to PYPI. push darsor github
91.96
14678018613 main version 1.0.0.0+vhdl push darsor github
91.95
14677998806 main update missed SV -> VHDL comment/naming changes push darsor github
91.95
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