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SystemRDL / PeakRDL-regblock-vhdl
92%

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DEFAULT BRANCH: main
Repo Added 24 Apr 2025 01:14PM UTC
Files 45
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  • main
  • dev/LGPLv3
  • dev/synth-tests
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  • single2slice
  • skiprwexternal
  • v1.0.0.0+vhdl
  • v1.0.0.1+vhdl
  • v1.0.0.2+vhdl
  • v1.0.0.3+vhdl
  • v1.1.0.0+vhdl
  • v1.1.1.0+vhdl

04 Nov 2025 02:32PM UTC coverage: 92.143% (+0.006%) from 92.137%
19072133657

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Single-bit std_logic to a slice (ghdl) (#28)

* peakrdl-regblock-vhdl used (0 => value) when assigning single-bit std_logic to a slice, instead of (low => value), causing “choice is out of index range” when low != 0

* Fix to use to_std_logic_vector instead of =>

799 of 929 branches covered (86.01%)

Branch coverage included in aggregate %.

2942 of 3131 relevant lines covered (93.96%)

2.82 hits per line

Relevant lines Covered
Build:
Build:
3131 RELEVANT LINES 2942 COVERED LINES
2.82 HITS PER LINE
Source Files on main
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  • Changed 1
  • Source Changed 0
  • Coverage Changed 1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
19072133657 main Single-bit std_logic to a slice (ghdl) (#28) * peakrdl-regblock-vhdl used (0 => value) when assigning single-bit std_logic to a slice, instead of (low => value), causing “choice is out of index range” when low != 0 * Fix to use to_std_logic_vect... push 04 Nov 2025 02:33PM UTC web-flow github
92.14
19057302901 main Switch to LGPLv3 license (#24) push 04 Nov 2025 03:58AM UTC web-flow github
92.14
17831916847 main Merge upstream/v1.1.1 into VHDL port push 18 Sep 2025 02:27PM UTC darsor github
92.14
17799211844 main Merge upstream/v1.1.0 into VHDL port push 17 Sep 2025 01:28PM UTC darsor github
92.14
17799079768 main Merge upstream/v1.1.0 into VHDL port push 17 Sep 2025 01:23PM UTC darsor github
92.14
14764755508 main version 1.0.0.3+vhdl push 30 Apr 2025 09:30PM UTC darsor github
91.96
14764711205 main VHDL updates for readthedocs documentation (#19) * update README * updated readthedocs for VHDL * updated many missed references to systemverilog exporter * added note in quick start about hdl-src/ files push 30 Apr 2025 09:27PM UTC web-flow github
91.96
14763659860 main Port synthesis tests to VHDL (#18) * update synthesis test runners for VHDL * don't use avalon intf pkg for flattened interface push 30 Apr 2025 08:24PM UTC web-flow github
91.96
14743637084 main version 1.0.0.2+vhdl (#13, #17) push 29 Apr 2025 11:58PM UTC darsor github
91.96
14740844555 main version 1.0.0.1+vhdl (#15, #17) No functional changes from v1.0.0.0, but now it should deploy to PYPI. push 29 Apr 2025 08:37PM UTC darsor github
91.96
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  • Repo on GitHub
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