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SystemRDL / PeakRDL-regblock-vhdl / 14759925589
92%
main: 92%

Build:
Build:
LAST BUILD BRANCH: v1.2.0.0+vhdl
DEFAULT BRANCH: main
Ran 30 Apr 2025 04:54PM UTC
Jobs 1
Files 43
Run time 6min
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30 Apr 2025 04:53PM UTC coverage: 91.962% (+0.006%) from 91.956%
14759925589

Pull #18

github

web-flow
Merge cdf6d5a10 into 5bd71cba6
Pull Request #18: Port synthesis tests to VHDL

759 of 886 branches covered (85.67%)

Branch coverage included in aggregate %.

2845 of 3033 relevant lines covered (93.8%)

5.63 hits per line

Jobs
ID Job ID Ran Files Coverage
1 14759925589.1 30 Apr 2025 07:28PM UTC 43
91.96
GitHub Action Run
Source Files on build 14759925589
  • Tree
  • List 43
  • Changed 1
  • Source Changed 0
  • Coverage Changed 1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses
  • Back to Repo
  • Pull Request #18
  • PR Base - main (#14743637084)
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