SystemRDL / PeakRDL-regblock-vhdl / 20557075623

Builds Branch Commit Type Ran Committer Via Coverage
20557075623 v1.2.0.0+vhdl fix read-buffered signed/fixedpoint fields push darsor github
92.15
20556698586 main fix read-buffered signed/fixedpoint fields push darsor github
92.15
20546802020 main fix read/write buffering in arrays of regfiles (#31) push darsor github
92.2
20546738636 main fix: correct assignment of single bit read-only storage-less fields (#33) * fix: correct assignment of single bit read-only storage-less fields * add tests for single-bit fields of all types --------- Co-authored-by: Dana Sorensen <dana.r.sore... push web-flow github
92.17
20546638300 fix-ro-singlebit-storageless Merge 6ff7f801c into adcd3ddd9 Pull #33 web-flow github
92.16
20540692408 main include hdl-src files in python wheel (#30) push darsor github
92.18
20513114033 main fix external block address width bug (#29) External regblock addr signals are now always a std_logic_vector, even when the width is 1. push darsor github
92.19
20511038480 main clarified upstream bugfix handling in issue template push web-flow github
92.29
20510926524 main fix jinja syntax error push darsor github
92.29
20478208721 fix-ro-singlebit-storageless Merge 8c766dfb1 into 074320873 Pull #33 web-flow github
92.11
19072133657 main Single-bit std_logic to a slice (ghdl) (#28) * peakrdl-regblock-vhdl used (0 => value) when assigning single-bit std_logic to a slice, instead of (low => value), causing “choice is out of index range” when low != 0 * Fix to use to_std_logic_vect... push web-flow github
92.14
19062329531 single2slice Merge fc5ea7b6f into 91895d552 Pull #28 web-flow github
92.14
19057302901 main Switch to LGPLv3 license (#24) push web-flow github
92.14
19050562345 single2slice Merge c085d77bc into 2238b14cd Pull #28 web-flow github
92.14
19050288379 skiprwexternal Merge 1291f4fa3 into 2238b14cd Pull #26 web-flow github
92.13