23185851492
92%
master: 92%

Ran 17 Mar 2026 08:57AM UTC

Jobs 1

Files 102

Run time 1min

Badge

Committed 17 Mar 2026 08:47AM UTC coverage: 92.484% (+0.003%) from 92.481%

Build Type

push

github

Committed by

Commit Message

Correct size and sign extension rules for Verilog case statement

Run Details

91 of 95 new or added lines in 4 files covered. (95.79%)

77868 of 84196 relevant lines covered (92.48%)

426660.67 hits per line

Lines	Coverage	∆	File
1	93.34	0.0%	src/jit/jit-core.c
3	97.8	-0.08%	src/jit/jit-irgen.c

ID	Job ID	Ran	Files	Coverage
1	23185851492.1	17 Mar 2026 08:56AM UTC	102	92.48	GitHub Action Run